PD44165092B_15 Datasheet, PDF (9/37 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION

μPD44165092B, μPD44165182B, μPD44165362B
Block Diagram
[μPD44165092B]
20
ADDRESS
R#
ADDRESS
20
W#
REGISTRY
& LOGIC
K
K#
W#
BW0#
9
D0 to D8
R#
K
K#
DATA
18
REGISTRY
& LOGIC
K
2²⁰ x 18
MEMORY
ARRAY
[μPD44165182B]
19
ADDRESS
R#
ADDRESS
19
W#
REGISTRY
& LOGIC
K
K#
W#
BW0#
BW1#
18
D0 to D17
R#
DATA
36
REGISTRY
& LOGIC
K
K#
K
2¹⁹ x 36
MEMORY
ARRAY
[μPD44165362B]
18
ADDRESS
R#
ADDRESS
18
W#
REGISTRY
& LOGIC
K
K#
W#
BW0#
BW1#
BW2#
BW3#
36
D0 to D35
R#
K
K#
DATA
72
REGISTRY
& LOGIC
K
2¹⁸ x 72
MEMORY
ARRAY
R10DS0017EJ0200 Rev.2.00
October 6, 2011
18
18
MUX
K
C, C#
OR
K, K#
36
36
MUX
K
C, C#
OR
K, #K
72
72
MUX
K
C, C#
OR
K, K#
9
Q0 to Q8
2
CQ,
CQ#
18
Q0 to Q17
2
CQ,
CQ#
36
Q0 to Q35
2
CQ,
CQ#
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