PD44165092B_15 Datasheet, PDF (12/37 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION

μPD44165092B, μPD44165182B, μPD44165362B
Byte Write Operation
[μPD44165092B]
Operation
Write D0 to D8
Write nothing
K
L→H
–
L→H
–
K#
–
L→H
–
L→H
BW0#
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[μPD44165182B]
Operation
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[μPD44165362B]
Operation
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
K
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
K#
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
−
L→H
BW0#
0
0
0
0
1
1
1
1
1
1
1
1
BW1#
0
0
1
1
0
0
1
1
1
1
1
1
BW2#
0
0
1
1
1
1
0
0
1
1
1
1
BW3#
0
0
1
1
1
1
1
1
0
0
1
1
Remarks 1. H : HIGH, L : LOW, → : rising edge.
2. Assumes a WRITE cycle was initiated. BW0# to BW3# can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
R10DS0017EJ0200 Rev.2.00
October 6, 2011
Page 12 of 36