PD44165092B_15 Datasheet, PDF (13/37 Pages) Renesas Technology Corp – 18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION

μPD44165092B, μPD44165182B, μPD44165362B
Bus Cycle State Diagram
W# = LOW
LOAD NEW
WRITE ADDRESS
AT K#
Always W# = LOW
WRITE DOUBLE
AT K#
LOAD NEW
READ ADDRESS
R# = LOW Always
READ DOUBLE
R# = LOW
W# = HIGH
R# = HIGH
W# = HIGH
R# = HIGH
Supply voltage
Supply voltage
WRITE PORT NOP
provided
Power UP
provided
READ PORT NOP
R_Init = 0
Remarks
1. The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
R10DS0017EJ0200 Rev.2.00
October 6, 2011
Page 13 of 36