H8S-2214 Datasheet, PDF (862/936 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2100 Series

Appendix B Internal I/O Register
TCNT0—Timer Counter
Bit
7
6
5
H'FF74(W)
H'FF75(R)
4
3
2
WDT0
WDT0
1
0
Initial value
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
RSTCSR—Reset Control/Status Register
H'FF76(W)
H'FF77(R)
Bit
:
7
6
5
4
3
2
WOVF RSTE RSTS
—
—
—
Initial value :
0
0
0
1
1
1
R/W
: R/(W)* R/W R/W
—
—
—
0
0
R/W R/W
WDT0
WDT0
1
0
—
—
1
1
—
—
Reset Select
0 Power-on reset
1 Manual reset
Reset Enable
0 No internal reset when TCNT overflows*
1 Internal reset is generated when TCNT overflows
Note: * The chip is not reset internally, but TCNT and
TCSR in WDT0 are reset.
Watchdog Overflow Flag
0 [Clearing condition]
• Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
• When TCNT overflows (from H'FF to H'00) in watchdog timer mode
Note: * Only 0 can be written, to clear the flag.
RSTCSR is write-protected by a password to prevent accidental overwriting.
For details see section 11.2.4, Notes on Register Access.
Rev.4.00 Sep. 18, 2008 Page 802 of 872
REJ09B0189-0400