H8S-2214 Datasheet, PDF (15/936 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2100 Series

Item
Page
10.7 Usage Notes 427
(1) Module Stop
Mode Settings
Figure 10.53
436
Contention between
TCNT Write and
Overflow
Revisions (See Manual for Details)
Description added
Figure amended
φ
TCNT write cycle
T₁
T₂
11.5.5 OVF Flag 451
Clear Operation in
Interval Timer Mode
12.2.7 Serial
468
Status Register
(SSR)
Bit 7—Transmit
Data Register
Empty (TDRE)
Bit 6—Receive Data
Register Full
(RDRF)
Address
Write signal
TCNT
TCFV flag
Newly added
TCNT address
H'FFFF
Prohibited
TCNT write data
M
Note added
Bit 7
TDRE
0
Description
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC* is activated by a TXI interrupt and writes data to TDR
Note: * This bit is cleared by DTC when DISEL = 0 and
furthermore the transfer counter is not 0.
Note added
Bit 6
RDRF
0
Description
[Clearing conditions]
(Initial value)
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC* is activated by an RXI interrupt and reads data from
RDR
Note: * This bit is cleared by DTC when DISEL = 0 and
furthermore the transfer counter is not 0.
Rev.4.00 Sep. 18, 2008 Page xv of lx
REJ09B0189-0400