H8S-2214 Datasheet, PDF (257/936 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2100 Series

Section 7 DMA Controller
• Block Transfer Mode
Bit 3 Bit
Bit 1 Bit 0
DTF3 DTF2 DTF1 DTF0 Description
0
0
0
0
—
(Initial value)
1
—
1
0
Activated by DREQ pin falling edge input^*
1
Activated by DREQ pin low-level input
1
0
0
Activated by SCI channel 0 transmission complete interrupt
1
Activated by SCI channel 0 reception complete interrupt
1
0
Activated by SCI channel 1 transmission complete interrupt
1
Activated by SCI channel 1 reception complete interrupt
1
0
0
0
Activated by TPU channel 0 compare match/input capture
A interrupt
1
Activated by TPU channel 1 compare match/input capture
A interrupt
1
0
Activated by TPU channel 2 compare match/input capture
A interrupt
1
—
1
0
0
—
1
—
1
0
—
1
—
Note: * Detected as a low level in the first transfer after transfer is enabled.
The same factor can be selected for more than one channel. In this case, activation starts with the
highest-priority channel according to the relative channel priorities. For relative channel priorities,
see section 7.5.10, DMAC Multi-Channel Operation.
Rev.4.00 Sep. 18, 2008 Page 197 of 872
REJ09B0189-0400