H8S-2214 Datasheet, PDF (270/936 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2100 Series

Section 7 DMA Controller
Operation in each mode is summarized below.
(1) Sequential Mode
In response to a single transfer request, the specified number of transfers are carried out, one byte
or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified
number of transfers have been completed. One address is specified as 24 bits, and the other as 16
bits. The transfer direction is programmable.
(2) Idle Mode
In response to a single transfer request, the specified number of transfers are carried out, one byte
or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified
number of transfers have been completed. One address is specified as 24 bits, and the other as 16
bits. The transfer source address and transfer destination address are fixed. The transfer direction
is programmable.
(3) Repeat Mode
In response to a single transfer request, the specified number of transfers are carried out, one byte
or one word at a time. When the specified number of transfers have been completed, the addresses
and transfer counter are restored to their original settings, and operation is continued. No interrupt
request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits.
The transfer direction is programmable.
(4) Normal Mode
• Auto-request
By means of register settings only, the DMAC is activated, and transfer continues until the
specified number of transfers have been completed. An interrupt request can be sent to the
CPU or DTC when transfer is completed. Both addresses are specified as 24 bits.
⎯ Cycle steal mode: The bus is released to another bus master every byte or word transfer.
⎯ Burst mode: The bus is held and transfer continued until the specified number of transfers
have been completed.
• External request
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. Both addresses are specified as 24 bits.
Rev.4.00 Sep. 18, 2008 Page 210 of 872
REJ09B0189-0400