H8S2426 Datasheet, PDF (840/1302 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 13 8-Bit Timers (TMR)
13.5.3 Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 13.7 Timing of Timer Output
13.5.4 Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1
and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this
operation.
φ
Compare match
signal
TCNT
N
H'00
Figure 13.8 Timing of Compare Match Clear
Rev. 1.00 Sep. 19, 2008 Page 812 of 1270
REJ09B0466-0100