H8S2426 Datasheet, PDF (105/1302 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

End of bus request
Bus request
Program execution state
Section 2 CPU
Bus-released state
Interrupt ^request
Sleep mode
Exception
handling state
RES = High
Reset state^*1
Reset state
External interrupt request
STBY = High,
RES = Low
Software standby
mode
Hardware standby
mode^*2
Power down state^*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 24, Power-Down Modes.
Figure 2.13 State Transitions
Rev. 1.00 Sep. 19, 2008 Page 77 of 1270
REJ09B0466-0100