H8S2426 Datasheet, PDF (315/1302 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

Section 6 Bus Controller (BSC)
(7) Idle Cycle in Case of Normal Space Access after DRAM Space Access
(a) Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.88 and 6.89 show examples of
idle cycle operation when the DRMI bit is set to 1.
When the DRMI bit is cleared to 0, an idle cycle is not inserted after DRAM space access even if
bits ICIS1 and ICIS0 are set to 1.
φ
Address bus
RD
RAS
UCAS, LCAS
DRAM space read
External address space read DRAM space read
T_p
T_r
T_c1
T_c2
T_i
T₁
T₂
T₃
T_i
T_c1
T_c2
Data bus
Idle cycle
Figure 6.88 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
Rev. 1.00 Sep. 19, 2008 Page 287 of 1270
REJ09B0466-0100