H8S2426 Datasheet, PDF (27/1302 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series

21.9 Serial Communication Interface Specification for Boot Mode........................................ 1064
Section 22 Boundary Scan (JTAG) .................................................................1089
Section 23 Clock Pulse Generator ...................................................................1091
23.1 Register Descriptions ....................................................................................................... 1092
23.1.1 System Clock Control Register (SCKCR) .......................................................... 1092
23.1.2 PLL Control Register (PLLCR).......................................................................... 1094
23.2 Oscillator.......................................................................................................................... 1095
23.2.1 Connecting a Crystal Resonator.......................................................................... 1095
23.2.2 External Clock Input........................................................................................... 1096
23.3 System-Clock PLL Circuit and Divider........................................................................... 1098
23.4 Usage Notes ..................................................................................................................... 1099
23.4.1 Notes on Clock Pulse Generator ......................................................................... 1099
23.4.2 Notes on Resonator............................................................................................. 1099
23.4.3 Notes on Board Design ....................................................................................... 1100
Section 24 Power-Down Modes ......................................................................1101
24.1 Register Descriptions ....................................................................................................... 1105
24.1.1 Standby Control Register (SBYCR) ................................................................... 1105
24.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 1107
24.1.3 Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL) ........................................................................ 1108
24.1.4 RAM Module Stop Control Registers H and L
(RMMSTPCRH, RMMSTPCRL)....................................................................... 1109
24.2 Operation ......................................................................................................................... 1110
24.2.1 Clock Division Mode.......................................................................................... 1110
24.2.2 Sleep Mode ......................................................................................................... 1111
24.2.3 Software Standby Mode...................................................................................... 1112
24.2.4 Hardware Standby Mode .................................................................................... 1115
24.2.5 Module Stop Function ........................................................................................ 1116
24.2.6 All Module Clocks Stop Mode ........................................................................... 1117
24.3 φ Clock Output Control.................................................................................................... 1118
24.4 SDRAMφ Clock Output Control ..................................................................................... 1119
24.5 Usage Notes ..................................................................................................................... 1120
24.5.1 I/O Port Status..................................................................................................... 1120
24.5.2 Current Dissipation during Oscillation Stabilization Standby Period................. 1120
24.5.3 EXDMAC, DMAC, and DTC Module Stop....................................................... 1120
24.5.4 On-Chip Peripheral Module Interrupts ............................................................... 1120
24.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR...................................... 1120
Rev. 1.00 Sep. 19, 2008 Page xxvii of xxviii