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HD64F2329BVTE25V Datasheet, PDF (834/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 18 Clock Pulse Generator
18.4 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (Ï).
18.5 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate Ï/2, Ï/4, Ï/8, Ï/16, and Ï/32.
18.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (Ï) or one of the medium-speed
clocks (Ï/2, Ï/4, Ï/8, Ï/16, or Ï/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
Rev.7.00 Feb. 14, 2007 page 800 of 1108
REJ09B0089-0700
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