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HD64F2329BVTE25V Datasheet, PDF (77/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 2 CPU
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU
can use.
Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function Instruction
Data
transfer
MOV
BWL BWL BWL BWL BWL BWL B BWL ⯠BWL ⯠⯠⯠â¯
POP, PUSH ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠WL
LDM, STM
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
L
MOVFPE,
â¯â¯
â¯
â¯â¯
â¯
â¯
B
â¯
â¯â¯
â¯
â¯
â¯
MOVTPE*1
Arithmetic ADD, CMP BWL BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
operations SUB
WL BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
ADDX, SUBX B
B
â¯
â¯â¯
â¯
â¯
â¯â¯
â¯
â¯â¯
â¯
â¯
ADDS, SUBS â¯
L
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
INC, DEC
⯠BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
DAA, DAS
⯠B â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
MULXU,
DIVXU
⯠BW ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
MULXS,
DIVXS
⯠BW ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
NEG
⯠BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
EXTU, EXTS ⯠WL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
TAS*2
â¯â¯ B â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
Logic
AND, OR,
operations XOR
BWL BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
NOT
⯠BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
Shift
⯠BWL ⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠â¯
Bit manipulation
â¯B
B â¯â¯â¯ B
B ⯠B â¯â¯â¯â¯
Branch
Bcc, BSR
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
â¯â¯
JMP, JSR
â¯â¯â¯â¯â¯â¯â¯â¯
â¯â¯â¯
â¯
RTS
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
System
control
TRAPA
RTE
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
SLEEP
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
LDC
B
B WWWWâ¯Wâ¯Wâ¯â¯â¯â¯
STC
â¯
B
W
W
W
Wâ¯Wâ¯W
â¯â¯â¯â¯
ANDC,
B
â¯
â¯
â¯â¯
â¯
â¯
â¯â¯
â¯
â¯â¯
â¯â¯
ORC, XORC
NOP
â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯â¯
Block data transfer
⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠⯠BW
Legend:
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Notes: 1. Cannot be used in the H8S/2319 Group.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev.7.00 Feb. 14, 2007 page 43 of 1108
REJ09B0089-0700
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