HD64F2329BVTE25V Datasheet, PDF (739/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 ROM
Table 17.50 Usable Parameters and Target Modes
Name of
Parameter
Abbre-
viation
Down- Initializa- Program-
load tion
ming
Erasure R/W
Alloca-
Initial Value tion
Download pass/ DPFR
fail result
—
—
—
R/W Undefined On-chip
RAM^*
Flash pass/fail FPFR
—
result
R/W Undefined R0L of
CPU
Flash
FPEFEQ —
programming/
erasing frequency
control
—
—
R/W Undefined ER0 of
CPU
Flash
FMPAR
—
—
multipurpose
address area
—
R/W Undefined ER1 of
CPU
Flash multi-
FMPDR
—
—
purpose data
destination area
—
R/W Undefined ER0 of
CPU
Flash erase
FEBS
—
—
—
block select
R/W Undefined ER0 of
CPU
Note: * One byte of start address of download destination specified by FTDAR
(1) Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the area as much as 4 kbytes starting from the start address specified by
FTDAR. For the address map of the on-chip RAM, see figure 17.69.
The download control is set by using the programming/erasing interface register. The return value
is given by the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM
specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by setting one byte of the
start address of the on-chip RAM area specified by FTDAR to a value other than the return value
of download (for example, H'FF) before the download start (before setting the SCO bit to 1). Refer
to item [e] in the User Program Mode Programming Procedure portion of section 17.24.2, for
information on the method for checking the download result.
Rev.7.00 Feb. 14, 2007 page 705 of 1108
REJ09B0089-0700