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HD64F2329BVTE25V Datasheet, PDF (573/1146 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Bit 7
TRGS1
0
1
Bit 6
TRGS0
0
1
0
1
Section 14 A/D Converter (8 Analog Input Channel Version)
Description
A/D conversion start by external trigger is disabled
(Initial value)
A/D conversion start by external trigger (TPU) is enabled
A/D conversion start by external trigger (8-bit timer) is enabled
A/D conversion start by external trigger pin (ADTRG) is enabled
Bits 5, 4, 1, and 0âReserved: These bits cannot be modified and are always read as 1.
Bit 3âClock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D
conversion time. See the description of the CKS bit for details.
Bit 2âReserved: A value of 1 must be written to this bit.
14.2.4 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see section 19.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 9âModule Stop (MSTP9): Specifies the A/D converter module stop mode.
Bit 9
MSTP9
0
1
Description
A/D converter module stop mode cleared
A/D converter module stop mode set
(Initial value)
Rev.7.00 Feb. 14, 2007 page 539 of 1108
REJ09B0089-0700
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