M66291GP Datasheet, PDF (83/126 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
3.2 FIFO Buffer
The M66291 has 6 endpoints available for bulk/interrupt/isochronous transfers in addition to endpoint 0 for
control transfer.
The M66291 is equipped with a total of 3 Kbytes FIFO that can be used as the buffer of the endpoint and can be
assigned arbitrary byte count in 64-byte unit against each endpoint.
3.2.1
FIFO Buffer Configuration
The endpoint buffer can be set for double buffer configuration and continuous transmit/receive mode. Each
buffer configuration is set by the registers as follows:
3.2.2
Endpoint 0:
•
•
•
Control Transfer Control Register
EP0 Packet Size Register
EP0_FIFO Continuous Transmit Data Length Register
Endpoint 1~6:
• EPi Configuration Register 0
• EPi Configuration Register 1
Buffer Access
The buffers of endpoints 0 to 6 can be accessed by the four data registers as follows:
<EP0_FIFO Data Register>
• Quantity : 1 piece
• Exclusively used for endpoint 0
<CPU_FIFO Data Register >
• Quantity : 1 piece
• Shared with endpoints 1 to 6 (specified by the CPU_EP bits)
<Dn_FIFO Data Register >
• Quantity : 2 pieces
• Shared with endpoints 1 to 6 (specified by the DMA_EP bits)
• Can be accessed by DMAC
These four data registers can be set independently to 8-bit/16-bit mode by the Octl bit.
Rev1.01 2004.11.01 page 83 of 122