M66291GP Datasheet, PDF (48/126 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
2.24 EP0_FIFO Control Register
Q EP0_FIFO Control Register (EP0_FIFO_CONTROL)
<Address : H’32>
b15 14
EP0_PID
0
0
-
-
-
-
13
IVAL
0
-
-
12 11 10
BCLR
0
-
-
E0req
1
-
-
CCPL
0
-
-
b
15~14
EP0_PID
Response PID
Bit name
13 IVAL
IN Buffer Set/OUT Buffer Status
12 BCLR
Buffer Clear
11 E0req
EP0_FIFO Ready
10 CCPL
Control Transfer Control
9 Reserved. Set it to “0”.
8~0 ODLN
Control Write Receive Data Length
9
8
7
6
5
4
3
2
1 b0
ODLN
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
<H/W reset : H'0800>
<S/W reset : ->
<USB bus reset : ->
Function
RW
00 : NAK
{{
01 : BUF
(Transmits response PID/data according to the state of
buffer etc,)
1x : STALL
<When set to control write transfer>
{{
Q Read
0: Disables the reading of data from the buffer
1: Enables the reading of data from the buffer
Q Write
Invalid (Ignored when written)
<When set to control read transfer>
Q Read
0 : Incomplete to write the data to buffer
1 : Complete to write the data to buffer
Q Write
0 : Invalid (Ignored when written)
1 : Complete to write the data to buffer
(Forced completion : Transmits the short packet)
<When set to control write transfer >
0{
Q Write
0 : Invalid (Ignored when written)
1 : Buffer clear (When the IVAL bit is set to "1")
<When set to control read transfer>
Q Write
0 : Invalid (Ignored when written)
1 : Buffer clear (Note : When the IVAL bit is set to “1”,
make sure to set the EP0_PID bits to “00” before
executing the aforesaid operations.)
0 : Enables to access EP0_FIFO Data Register etc,
{^×
1 : Disables to access EP0_FIFO Data Register etc,
0 : NAK response at status stage
{{
1 : Normal completion response at status stage
(ACK response/zero-length packet transmit)
00
Stores the receive data length in control write transfer
{^×
Rev1.01 2004.11.01 page 48 of 122