M66291GP Datasheet, PDF (26/126 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
2.10 Interrupt Enable Register 2
Q Interrupt Enable Register 2 (INT_ENABLE2)
<Address : H’14>
b15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
b
15~7
6~0
Bit name
Reserved. Set it to “0”.
EPB_NRE
Buffer Not Ready Interrupt Enable
9
8
7
6
5
4
3
2
1 b0
EPB_NRE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
<H/W reset : H'0000>
<S/W reset : H'0000>
<USB bus reset : ->
Function
RW
0 : Disable INTN bit set
00
{{
1 : Enable INTN bit set
b6 corresponds to EP6, ---b1 corresponds to EP1 and b0
corresponds to EP0.
(1) EPB_NRE (Buffer Not Ready Interrupt Enable) Bits (b6~b0)
These bits select whether to set the INTN bit to “1” or not when the EPB_NRDY bit is set to “1”.
Also refer to “3.1 Interrupt Function”.
Note : Do not set the corresponding bit of this register to “1” when the endpoint is set to isochronous transfer (set by
EPi _TYP bits).
Rev1.01 2004.11.01 page 26 of 122