M66291GP Datasheet, PDF (43/126 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
(3) CTRW (Control Write Transfer Continuous Receive Mode) Bit (b7)
This bit sets the receive mode at data stage of the control write transfer.
In case of unit receive mode, the receive completes after receiving one packet under the condition as follows:
• Receives the data equivalent to the size set by the EP0 Packet Size Register.
• Receives a short packet.
In case of continuous receive mode, the receipt completes after receiving several packets under the condition
as follows:
• Receives automatically the data equivalent to the size set by the EP0 Packet Size Register several
times and receives the data equivalent to 256 bytes.
• Receives the short packet.
The setting conditions of the IVAL bit of the EP0_FIFO Control Register change due to this bit.
(4) Ctr_Wr_Buf_Nmb (Control Write Buffer Start Number) Bits (b5~b0)
These bits set the beginning? block number of the buffer to be used in control write transfer. The block number
is a number for control by dividing the FIFO buffer into 64 byte sections (Note 1).
When the mode is set to unit receive (CTRW bit = “0”), the blocks set by these bits only are used and, from the
following block, it is possible to set to the buffer of a different endpoint.
When the mode is set to continuous receive (CTRW bit = “1”), the buffer equivalent to 256 bytes is used from
the block numbers set by these bits (Note 2).
Note 1: The M66291 is equipped with 3 Kbytes FIFO buffer and has blocks from H’0 to H’2F.
Note 2: Make sure that several endpoints do not get overlapped in the same buffer area.
Rev1.01 2004.11.01 page 43 of 122