M66291GP Datasheet, PDF (35/126 Pages) Renesas Technology Corp – ASSP (USB2.0 Device Controller)

M66291GP/HP
z Endpoint 1~6
{ When set to OUT buffer (EPi_DIR bit = “0”)
The condition for this bit to be set to “1” is as follows:
<The endpoint not specified by DMA_EP bits>
<The endpoint specified by DMA_EP bits with INTM bit set to “1”>
• When the IVAL bit of the endpoint changes from “0” to “1”
<The endpoint specified in DMA_EP bits with INTM bit set to “0”>
• When the buffer data including the received short packet (including the zero-length
packet) are all read out
The condition for this bit to be cleared to “0” differs according to the RDYM bit (Note):
• RDYM bit = “0” : When the IVAL bit of the endpoint changes from “1” to “0”
• RDYM bit = “1” : Writes “0” to this bit
Note :
When the INTM bit at the endpoint specified by the DMA_EP bit is set to “0”, the IVAL bit is
retained to “1”. Thus, it is necessary to write “1” to the BCLR bit and to clear the IVAL bit to
“0” when RDYM bit is set to “0”. Even when the RDYM bit is set to “1”, this bit can be cleared
by writing “0”. It is necessary to write “1” to the BCLR bit and to clear the IVAL bit.
{ When set to IN buffer (EPi_DIR bit = “1”)
The condition for this bit to be set to “1” is as follows:
<The endpoint not specified by DMA_EP bits>
<The endpoint specified by DMA_EP bits with INTM bit set to “1”>
• When the IVAL bit of the endpoint changes from “1” to “0”
• Or when EPi_DER bit is changed from “0” to “1”
<The endpoint specified by DMA_EP bits with INTM bit set to “0”>
This bit is not be set to “1”.
The condition for this bit to be cleared to “0” differs according to the RDYM bits:
• RDYM bit = “0” : When the IVAL bit of the endpoint changes from “0” to “1”
• RDYM bit = “1” : Writes “0” to this bit
Note : The IVAL bit is located per endpoint. For details, refer to “3.2.4 IVAL Bit and EPB_RDY Bit”.
USB bus
OUT token
SYNC PID Addr Endp CRC EOP
Data packet
SYNC PID Data CRC EOP
ACK packet
SYNC PID EOP
Interrupt output
Occurrence of buffer ready interrupt
because the buffer could be read
Figure 2.8 Examples of Buffer Ready Interrupt Occurrence Timing (OUT transfer)
Rev1.01 2004.11.01 page 35 of 122