M37221M4H_15 Datasheet, PDF (83/114 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
13. A-D COMPARISON CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted)
Symbol
—
—
Parameter
Resolution
Absolute accuracy
Test conditions
Limits
Unit
Min.
Typ.
Max.
6
bits
0
±1
±2
LSB
14. D-A CONVERSION CHARACTERISTICS
(VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 °C to 70 °C, unless otherwise noted)
Symbol
Parameter
—
Resolution
—
Absolute accuracy
tsu
Setting time
Ro
Output resistor
Note: Only M37221EASP/FP have a built-in D-A converter.
Test conditions
Limits
Unit
Min.
Typ.
Max.
6
bits
2
LSB
3
µs
1
2.5
4
kΩ
15. MULTI-MASTER I²C-BUS BUS LINE CHARACTERISTICS
Symbol
Parameter
Standard clock mode High-speed clock mode
Unit
Min.
Max.
Min.
Max.
tBUF
tHD; STA
tLOW
tR
Bus free time
Hold time for START condition
LOW period of SCL clock
Rising time of both SCL and SDA signals
4.7
1.3
µs
4.0
0.6
µs
4.7
1.3
µs
1000 20+0.1Cb
300
ns
tHD; DAT
tHIGH
tF
Data hold time
HIGH period of SCL clock
Falling time of both SCL and SDA signals
0
0
0.9
µs
4.0
0.6
µs
300
20+0.1Cb
300
ns
tSU; DAT
Data set-up time
250
100
ns
tSU; STA
tSU; STO
Set-up time for repeated START condition
Set-up time for STOP condition
4.7
0.6
µs
4.0
0.6
µs
Note: Cb = total capacitance of 1 bus line
SDA
tBUF
P
SCL
tLOW
tR
S
tHD;STA
tSU;STO
tF
Sr
P
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
Fig.15.1 Definition Diagram of Timing on Multi-master I²C-BUS
S : Start condition
Sr : Restart condition
P : Stop condition
Rev.1.00 Oct 01, 2002 page 81 of 110
REJ03B0134-0100Z