M37221M4H_15 Datasheet, PDF (61/114 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), the count starts at the rising edge
(falling edge) of HSYNC signal after the fixed cycle of the rising edge
(falling edge) of VSYNC signal. So the interval from the rising edge
(falling edge) of VSYNC signal to the rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) to avoid jitters.
The polarity of HSYNC and VSYNC signals can be select with the OSD
port control register (address 00EC16).
8 machine cycles
or more
VSYNC signal input
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
HSYNC
signal input
8 machine cycles
or more
0.125 to 0.25 [µs]
( at f(XIN) = 8MHz)
(See note 2)
12345
Not count
When bits 0 and 1 of the OSD port control register
(address 00EC16) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
Fig. 8.11.5 Supplement Explanation for Display Position
Rev.1.00 Oct 01, 2002 page 59 of 110
REJ03B0134-0100Z