M37221M4H_15 Datasheet, PDF (41/114 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8.6.6 START Condition Generation Method
When the ESO bit of the I²C control register (address 00DA16) is “1,”
execute a write instruction to the I²C status register (address 00D916)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
is output for 1 byte . The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.9 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
I²C statusregiste
write signal
SCL
SDA
BB flag
Setup
time
Setup
time
Hold time
Set time for
BB flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When the ESO bit of the I²C control register (address 00DA16) is “1,”
execute a write instruction to the I²C status register (address 00D916)
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP
condition will then be generated. The STOP condition generation tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 8.6.10 for the
STOP condition generation timing diagram, and Table 8.6.2 for the
START condition/STOP condition generation timing table.
I²Cstatus register
write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time for
BB flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Standard Clock Mode
Setup time
5.0 µs (20 cycles)
(START condition)
Setup time
4.25 µs (17 cycles)
(STOP condition)
Hold time
5.0 µs (20 cycles)
Set/reset time
for BB flag
3.0 µs (12 cycles)
High-speed Clock Mode
2.5 µs (10 cycles)
1.75 µs (7 cycles)
2.5 µs (10 cycles)
1.5 µs (6 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
Rev.1.00 Oct 01, 2002 page 39 of 110
REJ03B0134-0100Z