M37221M4H_15 Datasheet, PDF (44/114 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER

M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
S Slave address R/W A Data A Data A/A P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Data
A Data A/A P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Sr
Slave address
1st 7 bits
R/W
Data
A Data
A
P
7 bits
“0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master
I²C-BUS interface
(1) Read-modify-write instruction
Precautions for executing the read-modify-write instructions such as
SEB, and CLB, is for each register of the multi-master I²C-BUS inter-
face are described below.
•I²C data shift register (S0)
When executing the read-modify-write instruction for this register
during transfer, data may become an arbitrary value.
•I²C address register (S0D)
When the read-modify-write instruction is executed for this register
at detection of the STOP condition, data may become an arbitrary
______
value. It is because hardware changes the read/write bit (RBW) at
the timing.
•I²C status register (S1)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by hardware.
•I²C control register (S1D)
When the read-modify-write instruction is executed for this register
at detection of the START condition or at completion the byte trans-
fer, data may become an arbitrary value. Because hardware changes
the bit counter (BC0–BC2) at the timing.
•I²C clock control register (S2)
The read-modify-write instruction can be executed for this register.
From master to slave
From slave to master
(2) START condition generation procedure us-
ing multi-master
➀ Procedure example (The necessary conditions for the procedure
are described in ➁ to ➄ below).
•
•
LDA —
SEI
BBS 5,S1,BUSBUSY
BUSFREE:
STA S0
LDM #$F0, S1
CLI
•
•
BUSBUSY:
CLI
•
•
(Take out slave address value)
(Interrupt disabled)
(BB flag confirmation and branch process)
(Write slave address value)
(Trigger START condition generation)
(Interrupt enabled)
(Interrupt enabled)
➁ Use “STA,” “STX” or “STY” of the zero page addressing instruc-
tion for writing the slave address value to the I²C data shift register.
➂ Use “LDM” instruction for setting trigger of START condition gen-
eration.
④ Write the slave address value of ➁ and set trigger of START con-
dition generation as in ➂ continuously as shown in the procedure
example.
➄ Disable interrupts during the following three process steps:
• BB flag confirmation
• Write of slave address value
• Trigger of START condition generation
When the condition of the BB flag is bus busy, enable interrupts
immediately.
Rev.1.00 Oct 01, 2002 page 42 of 110
REJ03B0134-0100Z