TLC5944 Datasheet, PDF (8/34 Pages) Texas Instruments – 16-Channel, 12-Bit PWM LED Driver with 6-Bit Dot Correction and Pre-Charge FET

TLC5944
SBVS112 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
TERMINAL
NAME
PWP
SIN
5
RHB
2
SCLK
4
1
XLAT
DCSEL
GSCLK
BLANK
IREF
SOUT
XERR
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
VCC
VUP
GND
NC
3
32
6
3
25
24
2
31
27
26
24
23
23
22
7
4
8
5
9
6
10
7
11
8
12
9
13
10
14
11
15
14
16
15
17
16
18
17
19
18
20
19
21
20
22
21
28
27
26
25
1
30
—
12, 13,
28, 29
TERMINAL FUNCTIONS
I/O
DESCRIPTION
I Serial data input for grayscale and dot correction.
Serial data shift clock for GS shift register and DC shift register. Schmitt buffer input. The shift
register is selected by the DCSEL pin. Data present on the SIN pin are shifted into the shift
I register selected by DCSEL with the rising edge of the SCLK pin. Data in the selected shift
register are shifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB
data of the selected register appears on SOUT.
I
Data in the GS and DC shift register are moved to the respective data latch with a low-to-high
transition of this pin.
Shift register and data latch select. When DCSEL is low, SCLK/XLAT/SOUT are connected to the
I GS shift register and data latch. When DCSEL is high, SCLK/XLAT/SOUT are connected to the
DC shift register and data latch. DCSEL should not be changed while SCLK is high.
I
Reference clock for grayscale PWM control. If BLANK is low, then each rising edge of GSCLK
increments the grayscale counter for PWM control.
Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0
I
through OUT15) are forced off, the grayscale counter is reset to '0', and the grayscale PWM
timing controller is initialized. When BLANK is low, all constant current outputs are controlled by
the grayscale PWM timing controller.
I/O
Constant current value setting. OUT0 through OUT15 sink constant current is set to the desired
value by connecting an external resistor between IREF and GND.
O
Serial data output for GS, DC, and status information data (SID). This output is connected to the
MSB of the shift register selected by DCSEL.
O
Error output. Open-drain output. XERR goes low when LOD or TEF are set. XERR is in high
impedance when error free.
O
Constant current output. Each output can be tied to other outputs to increase the constant
current.
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
O Constant current output
— Power-supply voltage
— Pre-charge FET power supply
— Power ground
— No internal connection
8
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