TLC5944 Datasheet, PDF (19/34 Pages) Texas Instruments – 16-Channel, 12-Bit PWM LED Driver with 6-Bit Dot Correction and Pre-Charge FET

TLC5944
www.ti.com ...................................................................................................................................................................................................... SBVS112 – JUNE 2008
Grayscale (GS) Shift Register and Data Latch
The grayscale (GS) shift registers and data latches are each 192 bits in length, and set the PWM timing for each
constant current driver. See Table 3 for the ON time duty of each GS data bit. Figure 28 shows the shift register
and latch configuration. Refer to Figure 14 for the timing diagram for writing data into the GS shift register and
latch.
The driver on time is controlled by the data in the GS data latch. GS data present on the SIN pin are clocked into
the GS shift register with each rising edge of the GSCLK pin when DCSEL is low. Data are shifted in MSB first.
Data are latched from the shift register into the GS data latch with a rising edge on the XLAT pin. A DCSEL level
change is allowed when SCLK is low and 100 ns after the rising edge of XLAT.
When the device powers up, the data in the GS shift register and latches are not set to any default value.
Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANK
should be at a high level when powering on the device, because the constant current may be turned on as well.
All constant current output is off when BLANK is at a high level. The status information data (SID) byte is
overwritten on the most significant 18 bits of the grayscale shift register at the first rising edge of GSCLK after
XLAT goes low.
Grayscale Shift Register (12 Bits 16 Channels)
´
SOUT
(DCSEL = L)
GS Data for OUT15
MSB
191
180
¼ GS Data for OUT14 GS Data for OUT1
179
175
174
12
OUT15-Bit11
¼
(LOD-OUT15)
OUT15-Bit0 OUT14-Bit11
¼
(LOD-OUT4) (LOD-OUT3)
OUT14-Bit7 OUT14-Bit6
(TEF)
¼
(PTW)
OUT1-Bit0
GS Data for OUT0
LSB
11
0
¼ _OUT0-Bit11
OUT0-Bit0
SID Data are Overwritten Between Bits 191 and 174
SIN
SCLK
(DCSEL = L)
¼
¼
¼
¼
GS Data for OUT15
MSB
191
180
GS Data for OUT14 GS Data for OUT1
¼
179
12
GS Data for OUT0
LSB
11
0
¼ ¼ ¼ ¼ _OUT15-Bit11
OUT15-Bit0 OUT14-Bit11
OUT14-Bit7 OUT14-Bit6
OUT1-Bit0 OUT0-Bit11
OUT0-Bit0
XLAT
(DCSEL = L)
Grayscale Data Latch (12 Bits 16 Channels)
´
192 Bits
To PWM Timing Control Block
Figure 28. Grayscale Shift Register and Data Latch Configuration
Copyright © 2008, Texas Instruments Incorporated
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