TLC5944 Datasheet, PDF (12/34 Pages) Texas Instruments – 16-Channel, 12-Bit PWM LED Driver with 6-Bit Dot Correction and Pre-Charge FET

TLC5944
SBVS112 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
SIN
SCLK
XLAT
DCSEL
DC0
0A
T_H0
DC15
5B
DC15 DC15 DC15 DC15
4B 3B 2B 1B
T_SU0
f_CLK (SCLK)
DC0 DC0 DC0 DC0
3B 2B 1B
0B
T_WH0
DC15 DC15 DC15 DC15 DC15 DC15 DC14
5C 4C 3C 2C 1C 0C 5C
T_SU2
1 23 4 5
93 94 95 96
T_H2
T_WL0
T_H1 T_WH1
1 2 3456 7
T_SU4
Keep H Level
Latched Data
for Dot Correction
(Internal)
SOUT
OUTn
(Current)
Previous Data
t_D0
DC15 DC15 DC15 DC15 DC15 DC0 DC0 DC0 DC0
4A 3A 2A 1A 0A 3A 2A 1A 0A
GS DC15
MSB 5A
t_R0/t_F0
(I_OUTnH)
(I_OUTnL)
Latest Data
DC15
5B
DC15 DC15 DC15 DC15 DC15 DC14 DC14
4B 3B 2B 1B 0B 5B 4B
(I_OUTnH)
(I_OUTnL)
t_D7
Figure 15. Dot Correction Data Write Timing
The SCLK falling edge must be prior to the XLAT rising edge in case SID is read.
SIN
GS0
1
GS0
0
GS15 GS15 GS15 GS15 GS15
11A 10A 9A 8A 7A
GS14 GS14 GS14 GS14 GS14 GS14 GS14
9A 8A 7A 6A 5A 4A 3A
GS0 GS0
1A 0A
SCLK
191 192
T_{SU2 1 2 3 4 5 13 14 15 16 17 18 19 20 190 191 192}
T_H1 T_WH1 T_SU3
XLAT
DCSEL
SOUT
Keep L Level
GS15
11
t_D0
LOD LOD LOD LOD
15 14 13 12
LOD
3
LOD
2
LOD
1
LOD
0
TEF
TEF1
GS14
5
GS0 GS0 GS15
1
0 11A
SID are entered in GS shift register at the first rising edge of SCLK with low level
of DCSEL after XLAT. The SID readout consists of the saved LOD result at the
33rd GSCLK rising edge in the previous display period and the saved TEF data
and TEF1 at the rising edge of the first of SCLK after XLAT goes low.
Figure 16. Status Information Data Read Timing
12
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