R8C-20_1 Datasheet, PDF (78/501 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

R8C/20 Group, R8C/21 Group
8. Processor Mode
8. Processor Mode
8.1 Processor Modes
Single-chip mode can be selected as processor mode.
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
Table 8.1 Features of Processor Mode
Processor Mode
Single-chip mode
Accessible Areas
Pins Assignable as I/O Port Pins
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Processor Mode Register 0⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol
PM0
Address
0004h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
—
Reserved bits
Set to 0
(b2-b0)
RW
Softw are reset bit
PM03
The MCU is reset w hen this bit is set to 1.
When read, its content is 0.
RW
—
Nothing is assigned. If necessary, set to 0.
(b7-b4) When read, the content is 0.
—
NOTE:
1. Set the PRC1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM0 register.
Figure 8.1 PM0 Register
Processor Mode Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 _Symbol
PM1
Address
0005h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
—
Reserved bits
Set to 0
(b1-b0)
RW
WDT interrupt/reset sw itch bit
0 : Watchdog timer interrupt
PM12
1 : Watchdog timer reset⁽²⁾
RW
—
Nothing is assigned. If necessary, set to 0.
(b6-b3) When read, the content is 0.
—
—
Reserved bit
Set to 0
(b7)
RW
NOTES :
1. Set the PRC1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM1 register.
2. The PM12 bit is set to 1 by a program (it remains unchanged even if it is set to 0).
When the CSPRO bit in the CSPR register is set to 1 (selects count source protect mode), the PM12 bit is
automatically set to 1.
Figure 8.2 PM1 Register
Rev.2.00 Aug 27, 2008 Page 62 of 458
REJ09B0250-0200