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R8C-20_1 Datasheet, PDF (476/501 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES | |||
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REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual
Rev.
0.20
Date
Jun 28, 2006
Description
Page
Summary
12 2.8.7 Interrupt Enable Flag (I)
â2.8.7 Interrupt Enable Flag (I Flag)â â â2.8.7 Interrupt Enable Flag (I)â
revised.
2.8.8 Stack Pointer Select Flag (U)
â2.8.8 Stack Pointer Select Flag (U Flag)â â â2.8.8 Stack Pointer
Select Flag (U)â revised.
2.8.10 Reserved Bit
â2.8.10 Reserved Areaâ â â2.8.10 Reserved Bitâ revised.
13 Figure 3.1 Memory Map of R8C/20 Group;
âInternal ROMâ â âInternal ROM (program ROM)â revised
Address â1ZZZZhâ added.
NOTE revised.
Part Number revised.
14 Figure 3.2 Memory Map of R8C/21 Group;
âInternal ROMâ â âInternal ROM (program ROM)â revised.
âData areaâ â âData flashâ
âprogram areaâ â âprogram ROMâ revised
Address â1ZZZZhâ added.
NOTE2 added.
Part Number revised.
15 Table 4.1 SFR Information (1);
001Ch: 00h â 00h, 1000000b
0024h: TBD â Value when shipping
NOTES revised.
24 Figure 5.4 OFS Register, Function of the LVD1ON bit;
â~ after Hardware resetâ â â~ after resetâ revised.
NOTES revised.
25 5.1.1 When Power Supply is Stable (2) revised.
5.1.2 Power On (4) revised.
26 Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure
5.6 Example of Hardware Reset Circuit (Usage Example of External
Supply Voltage Detection Circuit) and Operation revised.
27 5.2 Power-On Reset Function, on the 2nd line;
âWhen a capacitor is ~ or more.â added.
Figure 5.7 Example of Power-On Reset Circuit and Operation revised.
NOTES revised.
28 5.3 Voltage Monitor 1 Reset(1); on the 8th line;
The LVD1ON bit in the OFS register can select to~ âafter a resetâ
added.
29 to 62 â6. Programmable I/O Portsâ â â6. Voltage Detection Circuitâ and
â7. Voltage Detection Circuitâ â â7. Programmable I/O Portsâ revised.
32 Figure 6.4 Registers VCA1 and VCA2;
VCA2 register revised.
33 Figure 6.5 VW1C Register revised.
C-2
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