R8C-20_1 Datasheet, PDF (488/501 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual
Rev.
Date
1.00 Nov 15, 2006
Page
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Description
Summary
10.4.1.3 Low-Speed On-Chip Oscillator Mode;
On the 2nd line from the bottom; “To enter wait mode from low-speed clock
mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low
consumption enabled) enables lower consumption current in wait mode.” added.
10.4.2.4 Exiting Wait Mode;
On the 13th line from the bottom; Figure 10.9 shows the Time from Wait Mode
to Interrupt Routine Execution. added.
Figure 10.9 Time from Wait Mode to Interrupt Routine Execution revised.
10.4.2.5 Reducing Internal Power Consumption and Figure 10.10 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit added
10.4.3.3 Exiting Stop Mode, on the 4th line;
“Figure 10.11 shows the Time from Stop Mode to Interrupt Routine Execution.”
added.
Figure 10.11 Time from Stop Mode to Interrupt Routine Execution added.
“Figure 10.10 State Transitions in Power Control Mode” →
“Figure 10.12 State Transitions in Power Control Mode” corrected.
10.5.1 How to Use Oscillation Stop Detection Function, on the 6th line;
“Figure 10.12” → “Figure 10.14” corrected.
On the 10th line; “Figure 10.11” → “Figure 10.13” corrected.
“Figure 10.11 ~” → “Figure 10.13 ~” corrected.
“Figure 10.12 ~” → “Figure 10.15 ~” corrected.
“10.6 Notes on Clock Generation Circuit” revised.
Figure 12.5 Registers INT0IC to INT3IC;
NOTE3; “INTOPL” → “INTiPL” corrected.
Figure 12.13 INTF Register revised
Figure 13.2 Registers OFS and WDC;
Option Function Select Register⁽¹⁾; NOTE2 revised.
Watchdog Timer Control Register revised.
Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode
Enabled);
NOTE2; “CSPRO” → “CSPROINI” corrected.
Figure 14.1 Block Diagram of Timer RA revised.
Figure 14.2 Registers TRACR and TRAIOC revised.
Figure 14.3 Registers TRAMR and TRAPRE
Timer RA Mode Register⁽¹⁾; NOTE added.
Timer RA Prescaler Register; NOTE1 revised.
Figure 14.4 TRA Register;
NOTE1 revised.
Table 14.2 Timer Mode Specifications;
“Write to Timer” revised.
Figure 14.5 TRAIOC Register in Timer Mode;
NOTES deleted.
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