R8C-20_1 Datasheet, PDF (51/501 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

R8C/20 Group, R8C/21 Group
6. Voltage Detection Circuit
6.2 Voltage Monitor 1 Reset
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset and Figure 6.7 shows an
Example of Voltage Monitor 1 Reset Operation. To use the voltage monitor 1 reset to exit stop mode, set the
VW1C1 bit in the VW1C register to 1 (digital filter disabled).
Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor 1 Reset
Step
1
2
3
4⁽¹⁾
5⁽¹⁾
6
7
8
9
When Using Digital Filter
When Not Using Digital Filter
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW1C7 bit in the VW1C register to
by the VW1F0 to VW1F1 bits in the VW1C 1
register
Set the VW1C1 bit in the VW1C register to Set the VW1C1 bit in the VW1C register to
“0” (digital filter enabled)
1 (digital filter disabled)
Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode)
Set the VW1C2 bit in the VW1C register to 0
Set the CM14 bit in the CM1 register to 0 −
(low-speed on-chip oscillator on)
Wait for the sampling clock of the digital − (no wait time)
filter x 4 cycles
Set the VW1C0 bit in the VW1C register to 1 (enables voltage monitor 1 reset)
NOTE:
1. When the VW1C0 bit is set to 0, procedures 3, 4 and 5 can be executed simultaneously (with 1
instruction).
Vdet1
VCC
When the VW1C1 bit is set
to 0 (digital filter enabled)
Internal reset signal
Sampling clock of
digital filter x 4 cycles
When the VW1C1 bit is set
to 1 (digital filter disabled)
and the VW1C7 bit is set
to 1
Internal reset signal
1
fOCO-S
x
32
1
fOCO-S
x
32
VW1C1 and VW1C7: Bits in VW1C register
The above applies to the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (enables voltage monitor 1 reset )
• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal is changed from “L” to “H”, the program is executed beginning with the address indicated by the
reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.7 Example of Voltage Monitor 1 Reset Operation
Rev.2.00 Aug 27, 2008 Page 35 of 458
REJ09B0250-0200