R8C-20_1 Datasheet, PDF (144/501 Pages) Renesas Technology Corp – MCU R8C FAMILY / R8C/2x SERIES

R8C/20 Group, R8C/21 Group
14. Timers
14.1.3 Event Counter Mode
Event counter mode is mode to count an external signal which inputs from the INT1/TRAIO pin (see Table
14.4 Event Counter Mode Specifications).
Figure 14.8 shows the TRAIOC Register in Event Counter Mode.
Table 14.4 Event Counter Mode Specifications
Item
Count Source
Count Operations
Divide Ratio
Count Start Condition
Count Stop
Conditions
Interrupt Request
Generation Timing
Specification
External signal which is input to TRAIO pin (active edge is selectable by a
program)
• Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is inherited
1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Write 1 (count starts) to the TSTART bit in the TRACR register
• Write 0 (count stops) to the TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register
When timer RA underflows [timer RA interrupt]
INT1/TRAIO Pin
Function
TRAO Pin Function
Read from Timer
Write to Timer
Select Functions
Count source input (INT1 interrupt input)
Programmable I/O port⁽¹⁾
The count value can be read by reading the TRA and TRAPRE registers
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control
during Count Operation).
• INT1 input polarity switch function
The TEDGSEL bit in the TRAIOC register can select the active edge of the
count source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
The pulse which inverts the polarity can be output from the TRAO pin each time
the timer underflows. (selected by the TOENA bit in the TRAIOC register)⁽¹⁾
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter
and select the sampling frequency.
NOTE:
1. The level of output pulse turn into the level when the pulse output starts by writing the TRAMR
register.
Rev.2.00 Aug 27, 2008 Page 128 of 458
REJ09B0250-0200