H8S-2626 Datasheet, PDF (760/1069 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 21B Power-Down Modes [H8S/2626 Group]
21B.9 Sub-Sleep Mode
21B.9.1 Sub-Sleep Mode
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR (WDT1) PSS bit = 1, CPU operation shifts to sub-sleep mode.
In sub-sleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are
also stopped. The contents of the CPUís internal registers, the data in internal RAM, and the
statuses of the internal supporting modules (excluding the SCI, ADC, HCAN) and I/O ports are
retained.
21B.9.2 Exiting Sub-Sleep Mode
Sub-sleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or
IRQ0 to IRQ5), or signals at the RES or STBY pins.
(1) Exiting Sub-Sleep Mode by Interrupts
When an interrupt occurs, sub-sleep mode is exited and interrupt exception processing starts.
In the case of IRQ0 to IRQ5 interrupts, sub-sleep mode is not cancelled if the corresponding
enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting
modules, the interrupt enable register has been set to disable the reception of that interrupt, or is
masked by the CPU.
(2) Exiting Sub-Sleep Mode by RES
For exiting sub-sleep mode by the RES pins, see, Clearing with the RES pins in section 21B.6.2,
Clearing Software Standby Mode.
(3) Exiting Sub-Sleep Mode by STBY Pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
Rev. 5.00 Jan 10, 2006 page 736 of 1042
REJ09B0275-0500