H8S-2626 Datasheet, PDF (340/1069 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
Bit 1
TGIEB
0
1
Description
Interrupt requests (TGIB) by TGFB bit disabled
Interrupt requests (TGIB) by TGFB bit enabled
(Initial value)
Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
Bit 0
TGIEA
0
1
Description
Interrupt requests (TGIA) by TGFA bit disabled
Interrupt requests (TGIA) by TGFA bit enabled
(Initial value)
10.2.5 Timer Status Register (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit
:7
6
5
4
3
2
1
0
—
—
—
TCFV TGFD TGFC TGFB TGFA
Initial value : 1
1
0
0
0
0
0
0
R/W
:—
—
—
R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Only 0 can be written, for flag clearing.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
:7
TCFD
Initial value : 1
R/W
:R
6
5
4
3
—
TCFU TCFV
—
1
0
0
0
—
R/(W)^* R/(W)^*
—
Note: * Only 0 can be written, for flag clearing.
2
1
0
—
TGFB TGFA
0
0
0
—
R/(W)^* R/(W)^*
Rev. 5.00 Jan 10, 2006 page 316 of 1042
REJ09B0275-0500