H8S-2626 Datasheet, PDF (677/1069 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 19 ROM (Preliminary)
number of loops in reprogramming processing is guaranteed not to exceed the maximum
value of the maximum programming count (N).
b. After write pulse application, a verify-read is performed in program-verify mode, and
programming is judged to have been completed for bits read as 0.
c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing
should be executed. If a bit for which programming has been judged to be completed is
read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.
5. The period for which the P1 bit in FLMCR1 is set (the write pulse width) should be changed
according to the degree of progress through the program/program-verify procedure. For
detailed wait time specifications, see section 22.6, Flash Memory Characteristics.
6. The program/program-verify flowchart for the H8S/2626 and H8S/2623 is shown in figure
19.11.
To cover the points noted above, bits on which reprogramming processing is to be executed,
and bits on which additional programming is to be executed, must be determined as shown
below.
Since reprogram data and additional-programming data vary according to the progress of the
programming procedure, it is recommended that the following data storage areas (128 bytes
each) be provided in RAM.
Reprogram Data Computation Table
Result of Verify-Read
after Write Pulse
(X)
(D) Application (V)
Result of Operation Comments
0
0
1
Programming completed: reprogramming
processing not to be executed
1
0
Programming incomplete: reprogramming
processing to be executed
1
0
1

1
Still in erased state: no action
Legend:
(D): Source data of bits on which programming is executed
(X): Source data of bits on which reprogramming is executed
Rev. 5.00 Jan 10, 2006 page 653 of 1042
REJ09B0275-0500