H8S-2626 Datasheet, PDF (727/1069 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Bit 7
SSBY
0
1
Section 21A Power-Down Modes [H8S/2623 Group]
Description
Shifts to sleep mode when the SLEEP instruction is executed in high-speed
mode or medium-speed mode.
(Initial value)
Shifts to software standby mode when the SLEEP instruction is executed in high-
speed mode or medium-speed mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time
for clock stabilization when shifting to high-speed mode or medium-speed mode by using a
specific interrupt or command to cancel software standby mode. With a quartz oscillator (table
21A.4), select a wait time of 8ms (oscillation stabilization time) or more, depending on the
operating frequency. With an external clock, there are no specific wait requirements.
Bit 6
STS2
0
1
Bit 5
STS1
0
1
0
1
Bit 4
STS0
0
1
0
1
0
1
0
1
Description
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states
(Initial value)
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode.
Bit 3
OPE
0
1
Description
In software standby mode, address bus and bus control signals are high-impedance.
In software standby mode, the output state of the address bus and bus control signals
is retained.
(Initial value)
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
Rev. 5.00 Jan 10, 2006 page 703 of 1042
REJ09B0275-0500