H8S2112 Datasheet, PDF (719/894 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 22 Flash Memory
(1) Bit-Rate-Adjustment State
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the
host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate
has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment
sequence is shown in figure 22.19.
Host
Boot program
H'00 (30 times maximum)
Measuring the
1-bit length
H'00 (completion of adjustment)
H'55
H'E6 (boot response)
(H'FF (error))
Figure 22.19 Bit-Rate-Adjustment Sequence
(2) Communications Protocol
After adjustment of the bit rate, the protocol for serial communications between the host and the
boot program is as shown below.
1. One-byte commands and one-byte responses
These one-byte commands and one-byte responses consist of the inquiries and the ACK for
successful completion.
2. n-byte commands or n-byte responses
These commands and responses are comprised of n bytes of data. These are selections and
responses to inquiries.
The program data size is not included under this heading because it is determined in another
command.
3. Error response
The error response is a response to inquiries. It consists of an error response and an error code
and comes two bytes.
Rev. 1.00 Mar. 18, 2008 Page 695 of 866
REJ09B0451-0100