H8S2112 Datasheet, PDF (459/894 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
• FDLL
Bit Bit Name Initial Value R/W
7 to 0 Bit 7 to All 0
R/W
bit 0
Description
Lower 8 bits of divisor latch
Baud rate = (Clock frequency input to baud rate generator) / (16 × divisor value)
15.3.6 Interrupt Enable Register (FIER)
FIER is a register that enables or disables interrupts. It is accessible when the DLAB bit in FLCR
is 0.
Bit Bit Name Initial Value R/W
7 to 4 
All 0
R
3
EDSSI
0
R/W
2
ELSI
0
R/W
1
ETBEI
0
R/W
0
ERBFI
0
R/W
Description
Reserved
This bit is always read as 0 and cannot be modified.
Modem Status Interrupt Enable
0: Modem status interrupt disabled
1: Modem status interrupt enabled
Receive Line Status Interrupt Enable
0: Receive line status interrupt disabled
1: Receive line status interrupt enabled
FTHR Empty Interrupt Enable
0: FTHR empty interrupt disabled
1: FTHR empty interrupt enabled
Receive Data Ready Interrupt Enable
A character timeout interrupt is included when the
FIFO is enabled.
0: Receive data ready interrupt disabled
1: Receive data ready interrupt enabled
Rev. 1.00 Mar. 18, 2008 Page 435 of 866
REJ09B0451-0100