H8S2112 Datasheet, PDF (608/894 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 19 LPC Interface (LPC)
• STR3 (TWRE = 0 and SELSTR3 = 1)
R/W
Bit Bit Name Initial Value Slave Host Description
7 DBU37 0
R/W R Defined by User
6 DBU36 0
R/W R The user can use these bits as necessary.
5 DBU35 0
R/W R
4 DBU34 0
R/W R
3 C/D3
0
R
R Command/Data Flag
When the host writes to IDR3, bit 2 of the I/O
address is written into this bit to indicate whether
IDR3 contains data or a command.
0: Content of input data register (IDR3) is a data
1: Content of input data register (IDR3) is a
command
2 DBU32 0
R/W R Defined by User
The user can use this bit as necessary.
1 IBF3
0
R
R Input Buffer Full
This bit is an internal interrupt source to the slave
(this LSI).
0: [Clearing condition]
When the slave reads IDR3
1: [Setting condition]
When the host writes to IDR3 in I/O write cycle
0 OBF3 0
R/(W)* R Output Buffer Full
0: [Clearing conditions]
• When the host reads ODR3 in I/O read cycle
• When the slave writes 0 to the OBF3 bit
1: [Setting condition]
When the slave writes to ODR3
Note: * Only 0 can be written to clear the flag.
Rev. 1.00 Mar. 18, 2008 Page 584 of 866
REJ09B0451-0100