H8S2112 Datasheet, PDF (526/894 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 16 I²C Bus Interface (IIC)
16.4.4 Master Receive Operation
In I²C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
Figure 16.10 shows the sample flowchart for the operations in master receive mode.
Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Clear IRIC flag in ICCR
Last receive? ^Yes
No
Read ICDR
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear IRIC flag in ICCR
[1] Select receive mode.
[2] Start receiving. The first read is a dummy read.
[5] Read the receive data (for the second and subsequent read)
[3] Wait for 1 byte to be received.
(Set IRIC at the rise of the 9th clock for the receive frame)
[4] Clear IRIC flag.
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear IRIC flag in ICCR
Set TRS = 1 in ICCR
Read ICDR
Set BBSY = 0 and
SCP = 0 in ICCR
End
[6] Set acknowledge data for the last reception.
[7] Read the receive data.
Dummy read to start receiving if the first frame is
the last receive data.
[8] Wait for 1 byte to be received.
[9] Clear IRIC flag.
[10] Read the receive data.
[11] Set stop condition issuance.
Generate stop condition.
Figure 16.10 Sample Flowchart for Operations in Master Receive Mode
Rev. 1.00 Mar. 18, 2008 Page 502 of 866
REJ09B0451-0100