H8S2112 Datasheet, PDF (575/894 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

KCLK
Software standby mode
and watch mode
PS2
Interrupt
control
Section 18 Keyboard Buffer Control Unit (PS2)
Interrupt control block
B
Falling edge
detection circuit _Interrupt
vector
generation
A
circuit
Interrupt request
to CPU
Figure 18.16 First KCLK Interrupt Path
(a) Interrupt timing in software standby mode and watch mode
KCLK
1
2
Software standby mode
and watch mode
internal signal
Interrupt internal signal
Interrupt generated
(b) When a transition to software standby mode or watch mode is performed while the KCLI is high
KCLK
4
5
6
Software standby mode
and watch mode
internal signal
Interrupt internal signal
Interrupt generated
(c) When a transition to software standby mode or watch mode is performed while the KCLK is low
KCLK
4
5
6
Software standby mode
and watch mode
internal signal
Interrupt internal signal
Interrupt generated
Figure 18.17 Interrupt Timing in Software Standby Mode and Watch Mode
Rev. 1.00 Mar. 18, 2008 Page 551 of 866
REJ09B0451-0100