H8S2112 Datasheet, PDF (107/894 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 4 Resets
Initial
Bit Bit Name Value R/W
Description
2 CKS2
0
R/W Clock Select 2 to 0
1 CKS1
0
0 CKS0
0
R/W Selects the clock source to be input to TCNT. The overflow
R/W ^{frequency for φ = 20 MHz and φSUB = 32.768 kHz is}
enclosed in parentheses.
When PSS = 0
000: φ/2 (frequency: 25.6 µs)
001: φ/64 (frequency: 819.2 µs)
010: φ/128 (frequency: 1.6 µs)
011: φ/512 (frequency: 6.6 µs)
100: φ/2048 (frequency: 26.2 µs)
101: φ/8192 (frequency: 104.9 µs)
110: φ/32768 (frequency: 419.4 µs)
111: φ/131072 (frequency: 1.68 s)
When PSS = 1
000: φSUB/2 (frequency: 16.5ms)
001: φSUB/4 (frequency: 31.3ms)
010: φSUB/8 (frequency: 62.5ms)
011: φSUB/16 (frequency: 125ms)
100: φSUB/32 (frequency: 250ms)
101: φSUB/64 (frequency: 500ms)
110: φSUB/128 (frequency: 1s)
111: φSUB/256 (frequency: 2s)
Note: 1. Only 0 can be written to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read
at least twice.
4.4 Pin Reset
This is a reset generated by the RES pin.
When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a
reset state. In order to firmly reset the LSI by pin reset, the RES pin should be held low at least for
20 ms at a power-on. When a reset is input during operation, the RES pin should be held low at
least for 20 states. Resetting the LSI initializes the internal state of the CPU and the registers of the
on-chip peripheral modules.
Rev. 1.00 Mar. 18, 2008 Page 83 of 866
REJ09B0451-0100