HD404358 Datasheet, PDF (68/102 Pages) Renesas Technology Corp – microcomputer has an A/D converter,

HD404358 Series
^{Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a}
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 54.
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ^← 0
SMR write
Yes
IFS = 1
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
State
Transmit clock
wait state
SCK pin (input)
1
SMR write
Transfer state
Transmit clock wait state
Transfer state
Noise
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.
IFS
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
Transmit clock error detection procedure
Figure 54 Transmit Clock Error Detection
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