HD404358 Datasheet, PDF (11/102 Pages) Renesas Technology Corp – microcomputer has an A/D converter,

HD404358 Series
Bit 3
IM0
0
(IM of INT₀)
Bit 2
IF0
(IF of INT₀)
Bit 1
RSP
(Reset SP bit)
1
IMTA
(IM of timer A)
IFTA
(IF of timer A)
IM1
(IM of INT₁)
Bit 0
IE
(Interrupt
enable flag)
IF1
(IF of INT₁)
$000
$001
2
IMTC
(IM of timer C)
IFTC
(IF of timer C)
IMTB
(IM of timer B)
IFTB
(IF of timer B)
$002
IMS
3
(IM of serial)
IFS
(IF of serial)
IMAD
(IM of A/D)
IFAD
(IF of A/D)
$003
Interrupt control bits area
Bit 3
32
Not used
RAME
33 (RAM enable
flag)
34
35
Bit 2
ADSF
(A/D start flag)
IAOF
(I_AD off flag)
Bit 1
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
Bit 0
Not used
$020
ICSF
(Input capture
status flag)
$021
Not used
$022
$023
Register flag area
IF: Interrupt request flag
IM: Interrupt mask
IE: Interrupt enable flag
SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
IE
IM
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
SEM/SEMD
Allowed
Not executed
Not executed
Allowed
Allowed
Not executed
REM/REMD
Allowed
Allowed
Allowed
Not executed
Inhibited
Not executed
TM/TMD
Allowed
Allowed
Inhibited
Inhibited
Allowed
Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
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