HD404344R Datasheet, PDF (68/102 Pages) Renesas Technology Corp – 4-bit microcomputer has an A/D converter

HD404344R Series/HD404394 Series
Transmit Clock Error Detection (External Clock Mode): Serial interface will malfunction if a spurious
pulse caused by external noise conflicts with a normal transmit clock during data transfer. A transmit clock
error of this type can be detected as shown in figure 44.
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer is completed and IFS is reset, writing to the serial mode register (SMR: $005)
changes the state from transfer to STS wait. At this time the serial interface is in the transfer state, and the
serial interrupt request flag (IFS: $003, bit 2) is set again, and therefore the error can be detected.
Transfer completion
(IFS ← 1)
Interrupts inhibited
IFS ← 0
SMR write
Yes
IFS = 1?
Transmit clock
error processing
No
Normal
termination
Transmit clock error detection flowchart
State
Transmit clock
wait state
Transfer state
Transmit clock wait state
Transfer state
SCK pin (input)
SMR write
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit
clock error. When SMR is
written, IFS is set.
IFS
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedure
Figure 44 Transmit Clock Error Detection
66