HD404344R Datasheet, PDF (64/102 Pages) Renesas Technology Corp – 4-bit microcomputer has an A/D converter

HD404344R Series/HD404394 Series
Serial Interface Operation
Selection and Changing of Serial Interface Operation Mode: The available settings for port mode
register A (PMRA: $004) and the serial mode register (SMR: $005) are shown in table 21. To change the
operating mode or to initialize the serial interface, write to the serial mode register.
The R0₀/SCK pin is controlled by writing data to serial mode register (SMR: $005). The R0₁/SI and
R0₂/SO pins are controlled by writing data to port mode register A (PMRA: $004).
Table 21 Serial Interface Operating Modes
SMR
Bit 3
1
PMRA
Bit 1
0
1
Bit 0
0
1
0
1
Operating Mode
Continuous clock output mode
Transmit mode
Receive mode
Transmit/receive mode
Setting Serial Clock Source: The transmit clock is set by writing to the serial mode register (SMR: $005)
and port mode register C (PMRC: $025).
Serial Data Setting: Serial data is sent by writing to the serial data register (SRL: $006 and SRU: $007).
Serial data can then be obtained by reading the serial data register. Serial data is shifted by the transmit
clock.
The output of the SO pin is undefined until the first serial data is output after an MCU reset, or until the
output level control is performed during an idle state.
Transfer Control: Serial interface operation is initiated by an STS instruction. The octal counter is reset
by the STS instruction to 000 and then incremented by one by the rising edge of the transmit clock. If eight
rising edges from the transmit clock is input or the serial data transfer is cut-off, the counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the serial data transfer stops.
As for using the built-in prescaler output for the transmit clock, selection for the transmit clock frequency
can be from 4t_cyc to 8192t _cyc by setting bits 2 to 0 (SMR2–SMR0) of the serial mode register (SMR: $005)
and bit 0 (PMRC0) of port mode register C (PMRC: $025). Writing to these registers for the setting of the
transmit clock is shown in table 22.
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