HD404344R Datasheet, PDF (65/102 Pages) Renesas Technology Corp – 4-bit microcomputer has an A/D converter

HD404344R Series/HD404394 Series
Table 22 Transmit Clock Selection (Prescaler Output)
PMRC
Bit 0
0
SMR
Bit 2
0
1
1
0
1
Bit 1
0
1
0
0
1
0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
Prescaler Division Ratio
÷ 2048
÷ 512
÷ 128
÷ 32
÷8
÷2
÷ 4096
÷ 1024
÷ 256
÷ 64
÷ 16
÷4
Transmit Clock Frequency
4096t_cyc
1024t_cyc
256t_cyc
64t_cyc
16t_cyc
4t_cyc
8192t_cyc
2048t_cyc
512t_cyc
128t_cyc
32t_cyc
8t_cyc
Serial Interface Operating States: The serial interface has the following operating states shown in figure
42, both in external clock mode and internal clock mode.
 STS wait state
 Transmit clock wait state
 Transfer state
 Continuous clock output (internal clock mode only)
• STS wait state: The serial interface is put into the STS wait state by an MCU reset (00, 10 in figure 42).
While in this state, the serial interface is initialized and does not operate, even if a transmit clock is
provided. If an STS instruction is executed while in this state (01, 11), the serial interface transfers to
the transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state period starts from when an STS instruction is
executed until the first transmit clock falling edge. While in the transmit clock wait state, if the transmit
clock is input (02, 12), the octal counter is incremented by the transmit clock, the data in the serial data
register shifts, and the serial interface enters the transfer state. However, note that if continuous clock
output mode is selected in internal clock mode, the serial interface does not enter transfer state but
enters continuous clock output state (17).
By writing to the serial mode register (SMR: $005) (04, 14) while in the transmit clock wait state, the
serial interface changes to the STS wait state.
• Transfer state: The transfer state period starts from the first falling edge of the transmit clock to the
eighth rising edge of the transmit clock. While in the transfer state, if an STS instruction is executed or
eight pulses of the transmit clock is applied, the octal counter will reset to 000 and the state will change.
If an STS instruction is executed (05, 15), the state changes to the transmit clock wait state. After the
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