HD404344R Datasheet, PDF (66/102 Pages) Renesas Technology Corp – 4-bit microcomputer has an A/D converter

HD404344R Series/HD404394 Series
eight pulses of the transmit clock, the state changes to the transmit clock wait state for the external clock
mode (03). Also, the state changes to the STS wait state for the internal clock mode (13). In the internal
clock mode, the transmit clock stops after eight pulses of the transmit clock are output.
While in the transfer state, if the serial mode register (SMR: $005) (06, 16) is written to, the serial
interface is initialized and the state changes to the STS wait state.
After the transfer state has changed to another state, the octal counter is reset to 000 and the serial
interrupt request flag (IFS: $003, 2) is set.
• Continuous clock output state (internal clock mode only): Continuous clock output state is the state in
which only the transmit clock from the SCK pin is output without data transfer. This can be done only
while in internal clock mode.
When the status of the 1 and 0 bits (PMRA1, PMRA0) of port mode register A (PMRA: $004) is 00
while in transmit clock wait state, the state can be changed to continuous clock output state by enabling
the transmit clock (17). By writing to the serial mode register (SMR: $005) while in continuous clock
output state (18), the state will change to the STS wait state.
STS wait state
(Octal counter = 000,
transmit clock disabled)
MCU reset 00
SMR write 04
STS instruction 01
SMR write (IFS ^← 1) 06
Transmit clock wait state
(Octal counter = 000)
Transmit clock 02
8 transmit clocks 03 or STS instruction 05 (IFS ← 1)
Transfer state
(Octal counter = 000)
External clock mode
SMR write 18
STS wait state
(Octal counter = 000,
transmit clock disabled)
MCU reset 10
Continuous clock output state
(PMRA 0, 1 = 0, 0)
SMR write 14
STS instruction 11
Transmit clock 17
Transmit clock wait state
(Octal counter = 000)
Transmit clock 12
STS instruction 15 (IFS ← 1)
8 transmit clocks 13 or
SMR write (IFS ← 1) 16
Transfer state
(Octal counter = 000)
Internal clock mode
Note: Refer to the operating states section for the corresponding encircled numbers.
Figure 42 Serial Interface State Transitions
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