H8S2189R Datasheet, PDF (633/812 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 18 Flash Memory (0.18-µm F-ZTAT Version)
(1) On-Chip RAM Address Map when Programming/Erasing is Executed
Part of the procedure program that is made by the user, like the download request,
programming/erasing procedure, and determination of the result, must be executed in the on-chip
RAM. The on-chip program that is to be downloaded is all in the on-chip RAM. Note that areas in
the on-chip RAM must be controlled so that these parts do not overlap.
Figure 18.10 shows the area where a program is downloaded.
Area where program
is downloaded
(Size: 2 Kbytes)
This area cannot be
used during the
programming/
erasing processing.
<On-chip RAM>
Area that can be used by user*
Address
RAMTOP
DPFR
(Return value: 1 byte)
FTDAR setting
System area
(15 bytes)
Programming/erasing program entry
Initialization program entry
FTDAR setting + 16
FTDAR setting + 32
Initialization + programming program
or
Initialization + erasing program
FTDAR setting + 2 Kbytes
Area that can be used by user*
RAMEND
Note: * Differs according to the area specified by FTDAR since the on-chip RAM area
in this LSI is split into H'FFD880 to H'FFEFFF and H'FFFF00 to H'FFFF7F.
Figure 18.10 RAM Map when Programming/Erasing is Executed
Rev. 2.00 Aug. 03, 2005 Page 591 of 766
REJ09B0223-0200