H8S2189R Datasheet, PDF (157/812 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series

Section 5 Interrupt Controller
5.6.4 Interrupt Response Times
Table 5.9 shows interrupt response times − the intervals between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine.
Table 5.9 Interrupt Response Times
No. Execution Status
Normal Mode
Advanced Mode
1
Interrupt priority determination*¹
3
3
2
Number of wait states until executing instruction 1 to 21
ends*²
1 to 21
3
Saving of PC and CCR in stack
2
2
4
Vector fetch
1
2
5
Instruction fetch*³
2
2
6
Internal processing*⁴
2
2
Total (using on-chip memory)
11 to 31
12 to 32
Notes: 1. Two states in case of internal interrupt.
2. Refers to MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and prefetch of interrupt handling routine.
4. Internal processing after interrupt acceptance and internal processing after vector fetch.
Rev. 2.00 Aug. 03, 2005 Page 115 of 766
REJ09B0223-0200